1. The Field of the Invention
This invention relates to integrated circuit structures. More particularly, the present invention relates to capacitor structures used with dynamic random access memory cells formed on integrated circuits.
2. The Background Art
The miniaturization of electrical components and their integration on a single piece of semiconductor material has been the catalyst of a world-wide information revolution. As integrated circuit technology has progressed, it has been possible to store ever increasing amounts of digital data in a smaller space at less expense and still access the data randomly, quickly, and reliably. Central to this greatly increased ability to store and retrieve data has been the dynamic random access memory, or DRAM, fabricated as an integrated circuit.
In the case of mass produced DRAMs, the cost per bit of memory provided has historically decreased as the number of bits which can be reliably stored on each integrated circuit has increased. Thus, it is advantageous to pack as many memory cells as practically possible on each square unit of planar area available on an integrated circuit.
The memory cells of DRAMs are comprised of two main components: a transistor and a capacitor. The capacitor of each memory cell functions to store an electrical charge representing a digital value, e.g., a charged capacitor representing a 1 and a discharged capacitor representing a 0, with the transistor acting as a switch to connect the capacitor to the "outside world" via decoding and other circuitry.
The state of the art has progressed to the point where the transistor can be made much smaller than the capacitor. In order to function properly, the capacitor must possess a minimum amount of capacitance. Generally, it is desirable that each memory cell capacitor, also referred to as a "storage node," possess as much capacitance as possible, but at least 20.times.10.sup.-15 farads, and preferably more than 60.times.10.sup.-15 farads, of charge storage capacity. If a capacitor exhibits too little capacitance, it will loose any charge placed upon it too rapidly causing errors in data storage.
The capacitive value of a capacitor is dependent upon the dielectric constant of the material placed between the plates of the capacitor, the distance between the plates, and the effective area of the plates. In many cases, the material used as a dielectric between the plates is limited to only a few materials. Also, the minimum distance between the capacitor plates is generally limited to a particular value where the number of defects are kept to an acceptably low value. Thus, the one parameter which can be varied to obtain an increased storage capacity is the area of the plates.
Thus, it is a goal of DRAM designers to increase the area of the capacitor plates as much as possible. Concurrently, it is also a goal to reduce the planar area occupied by each capacitor to a minimum so that as many memory cells as possible can be packed onto a single integrated circuit. Thus, various three dimensional structures have been proposed and adopted in the art to maintain the value of a capacitor at a desirably high level while keeping the planar area devoted to the capacitor at a minimum.
Among the proposed schemes for maintaining cell capacitance while decreasing the planar area devoted to the cell is one described in Lu, N. C. C., "Advanced Structures for Dynamic RAMs" IEEE Circuits and Devices Magazine 27-35 (Jan. 1989) and described as a "trench-transistor cell." In the trench-transistor cell described in the Lu paper, the capacitor cell becomes a vertical structure with the access transistor also becoming vertical and placed above the cell capacitor. While the described trench cell provides greater capacitor plate area in a small planar area when compared to planar capacitor structures, the described trench structure provides only a modest increase in charge storage capacity, as well as additional difficulties during fabrication.
In view of the foregoing, it would be an advance in the art to provide a structure and method for forming a capacitor structure on an integrated circuit which provides increased capacitance in a decreased planar area. It would be another advance in the art to provide a structure and method for forming a capacitor structure on an integrated circuit which provides a high capacitance per square unit of planar area and which can be reliably manufactured and operated. It would be another advance in the art to provide an improved structure and method for forming a capacitor structure on an integrated circuit which is particularly adapted for integration into DRAM memory cells.